DSP 28335 开发之SCI

文章来源:未知 时间:2016年05月15日

(1)初始化SCI:

void init_SCI(void)

{/* initialize SCI & FIFO registers */

EALLOW;

/*

* Initialize SCI_A with following parameters:

*BaudRate:

*CharacterLengthBits: 8

*EnableLoopBack: 0

*NumberOfStopBits: 1

*ParityMode: None

*SuspensionMode: Free_run

*CommMode: Raw_data

*/

SciaRegs.SCICCR.bit.STOPBITS = 0;//Number of stop bits. (0: One stop bit, 1: Two stop bits)

SciaRegs.SCICCR.bit.PARITY = 0;//Parity mode (0: Odd parity, 1: Even parity)

SciaRegs.SCICCR.bit.PARITYENA = 0;//Enable Pary Mode

SciaRegs.SCICCR.bit.LOOPBKENA = 0;//Loop Back enable

SciaRegs.SCICCR.bit.ADDRIDLE_MODE = 0;//ADDR/IDLE Mode control

SciaRegs.SCICCR.bit.SCICHAR = 7;//Character length

SciaRegs.SCICTL1.bit.RXERRINTENA = 0;//Disable receive error interrupt

SciaRegs.SCICTL1.bit.SWRESET = 1;//Software reset

SciaRegs.SCICTL1.bit.TXENA = 1;// SCI transmitter enable

SciaRegs.SCICTL1.bit.RXENA = 1;// SCI receiver enable

SciaRegs.SCIHBAUD = 0;

SciaRegs.SCILBAUD = 39;

//Free run, continue SCI operation regardless of suspend

SciaRegs.SCIPRI.bit.FREE = 1;// Free emulation mode control

SciaRegs.SCIPRI.bit.SOFT = 0;// Interrupt priority select

SciaRegs.SCIFFCT.bit.ABDCLR = 0;

SciaRegs.SCIFFCT.bit.CDC = 0;

SciaRegs.SCIFFTX.bit.SCIRST = 1;// SCI reset rx/tx channels

SciaRegs.SCIFFTX.bit.SCIFFENA = 1;// SCI FIFO enhancements are enabled.

SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;// Re-enable transmit FIFO operation.

SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;// Re-enable receive FIFO operation.

/*

* Initialize SCI_B with following parameters:

*BaudRate:

*CharacterLengthBits: 8

*EnableLoopBack: 0

*NumberOfStopBits: 1

*ParityMode: None

*SuspensionMode: Free_run

*CommMode: Raw_data

*/

ScibRegs.SCICCR.bit.STOPBITS = 0;//Number of stop bits. (0: One stop bit, 1: Two stop bits)

ScibRegs.SCICCR.bit.PARITY = 0;//Parity mode (0: Odd parity, 1: Even parity)

ScibRegs.SCICCR.bit.PARITYENA = 0;//Enable Pary Mode

ScibRegs.SCICCR.bit.LOOPBKENA = 0;//Loop Back enable

ScibRegs.SCICCR.bit.ADDRIDLE_MODE = 0;//ADDR/IDLE Mode control

ScibRegs.SCICCR.bit.SCICHAR = 7;//Character length

ScibRegs.SCICTL1.bit.RXERRINTENA = 0;//Disable receive error interrupt

ScibRegs.SCICTL1.bit.SWRESET = 1;//Software reset

ScibRegs.SCICTL1.bit.TXENA = 1;// SCI transmitter enable

ScibRegs.SCICTL1.bit.RXENA = 1;// SCI receiver enable

ScibRegs.SCIHBAUD = 0;

ScibRegs.SCILBAUD = 39;

//Free run, continue SCI operation regardless of suspend

ScibRegs.SCIPRI.bit.FREE = 1;// Free emulation mode control

ScibRegs.SCIPRI.bit.SOFT = 0;// Interrupt priority select

ScibRegs.SCIFFCT.bit.ABDCLR = 0;

ScibRegs.SCIFFCT.bit.CDC = 0;

ScibRegs.SCIFFTX.bit.SCIRST = 1;// SCI reset rx/tx channels

ScibRegs.SCIFFTX.bit.SCIFFENA = 1;// SCI FIFO enhancements are enabled.

ScibRegs.SCIFFTX.bit.TXFIFOXRESET = 1;// Re-enable transmit FIFO operation.

ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;// Re-enable receive FIFO operation.

/*

* Initialize SCI_C with following parameters:

*BaudRate:

*CharacterLengthBits: 8

*EnableLoopBack: 0

*NumberOfStopBits: 1

*ParityMode: None

*SuspensionMode: Free_run

*CommMode: Raw_data

*/

ScicRegs.SCICCR.bit.STOPBITS = 0;//Number of stop bits. (0: One stop bit, 1: Two stop bits)

ScicRegs.SCICCR.bit.PARITY = 0;//Parity mode (0: Odd parity, 1: Even parity)

ScicRegs.SCICCR.bit.PARITYENA = 0;//Enable Pary Mode

ScicRegs.SCICCR.bit.LOOPBKENA = 0;//Loop Back enable

ScicRegs.SCICCR.bit.ADDRIDLE_MODE = 0;//ADDR/IDLE Mode control

ScicRegs.SCICCR.bit.SCICHAR = 7;//Character length

ScicRegs.SCICTL1.bit.RXERRINTENA = 0;//Disable receive error interrupt

ScicRegs.SCICTL1.bit.SWRESET = 1;//Software reset

ScicRegs.SCICTL1.bit.TXENA = 1;// SCI transmitter enable

ScicRegs.SCICTL1.bit.RXENA = 1;// SCI receiver enable

ScicRegs.SCIHBAUD = 0;

ScicRegs.SCILBAUD = 39;

//Free run, continue SCI operation regardless of suspend

ScicRegs.SCIPRI.bit.FREE = 1;// Free emulation mode control

ScicRegs.SCIPRI.bit.SOFT = 0;// Interrupt priority select

ScicRegs.SCIFFCT.bit.ABDCLR = 0;

ScicRegs.SCIFFCT.bit.CDC = 0;

ScicRegs.SCIFFTX.bit.SCIRST = 1;// SCI reset rx/tx channels

ScicRegs.SCIFFTX.bit.SCIFFENA = 1;// SCI FIFO enhancements are enabled.

ScicRegs.SCIFFTX.bit.TXFIFOXRESET = 1;// Re-enable transmit FIFO operation.

ScicRegs.SCIFFRX.bit.RXFIFORESET = 1;// Re-enable receive FIFO operation.

EDIS;

}

(2)初始化SCI相关的GPIO

void init_SCI_GPIO(void)

{

EALLOW;

/*GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;//Enable pull-up for GPIO28

GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //Configure GPIO28 as SCIRXDA

GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;//Enable pull-up for GPIO29

GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //Configure GPIO29 as SCITXDA*/

GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0;//Enable pull-up for GPIO23

GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; //Configure GPIO23 as SCIRXDB

GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0;//Enable pull-up for GPIO22

GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; //Configure GPIO22 as SCITXDB

/*GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0;//Enable pull-up for GPIO62

GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; //Configure GPIO62 as SCIRXDA

GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0;//Enable pull-up for GPIO63

GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; //Configure GPIO63 as SCITXDA*/

EDIS;

}

(3)初始化配置:

init_SCI();

init_SCI_GPIO();

(4)应用函数

/*

* Receive character(s) from the SCIa

* Received character(s) will be write to rcvBuff.

* Return 0 if characters are received with no error.

* Return 1 if waiting timeout.

* Return 2 if data error.(receiving timout or checksum error)

* Return 3 if a parity error occured.

* Return 4 if a frame error occured.

*/

int scia_rcv(char *rcvBuff, int buffLen, int loopMode)

{

int i;

unsigned int cnt = 0;

unsigned int maxcnt;

if (loopMode == LONGLOOP) {

maxcnt = RCVMAXCNTL;

} else {

maxcnt = RCVMAXCNTS;

}

for (i = 0; i maxcnt)

return TIMEOUT;

} else {

if (cnt++ > RCVMAXCNTL)

return TIMEOUT;

}

}

rcvBuff[i] = SciaRegs.SCIRXBUF.all;

if (SciaRegs.SCIRXST.bit.FE)

return FRAMERR;

if (SciaRegs.SCIRXST.bit.PE)

return PRTYERR;

if ((SciaRegs.SCIRXST.bit.RXWAKE ==1) && (SciaRegs.SCIRXST.bit.RXERROR == 1)

) {

SciaRegs.SCICTL1.bit.SWRESET = 1;

SciaRegs.SCICTL1.bit.SWRESET = 0;

SciaRegs.SCICTL1.bit.SWRESET = 1;

}

}

return NOERROR;

}

int byteswap_L8cmp(unsigned int* outdata, char* recdata, int inportWidth, int

typeLen)

{

int i, j;

int numWrd = (inportWidth * typeLen)/2;// number of words (16 bit length) to receive

/* Little Endian, 8bit swap */

for (i = 0; i >(8*j);

}

}

return 0;

}

char txString0[31]="2号板,CAN_A_1接收数据:0x;";

char txString1[31]="2号板,CAN_A_2接收数据:0x;";

char txString2[31]="2号板,CAN_A_3接收数据:0x;";

char txString3[31]="2号板,CAN_A_4接收数据:0x;";

char *String_END = "\n";

scib_xmit((char*)txString0, 31);

scib_xmit(String_END, 1);

scib_xmit((char*)txString1, 31);

scib_xmit(String_END, 1);

scib_xmit((char*)txString2, 31);

scib_xmit(String_END, 1);

scib_xmit((char*)txString3, 31);

scib_xmit(String_END, 1);

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