Verilog is very widely used for RTL synthesis, even though it wasn’t designed as a synthesis language. It is very easy to write Verilog code that simulates correctly, and yet produces an incorrect design.For example, it is easy unintentionally to infer transparent latches. One of the ways in which SystemVerilog addresses this is through the introduction of new always keywords: always_comb, always_latch and always_ff.

always_comb is used to describe combinational logic. It implicitly creates a complete sensitivity list by looking at the variables and nets that are read in the process, just like always @* in Verilog-2001.


if (sel)

f = x;


f = y;

n addition to creating a complete sensitivity list automatically, it recursively looks into function bodies and inserts any other necessary signals into the sensitivity list. It also is defined to enforce at least some of the rules for combinational logic, and it can be used as a hint (particularly by synthesis tools) to apply more rigorous synthesis style checks.Finally, always_comb adds new semantics: it implicitly puts its sensitivity list at the end of the process, so that it is evaluated just once at time zero and therefore all its outputs take up appropriate values before simulation time starts to progress.

always_latch and always_ff are used for infering transparent latches and flip-flops respectively. Here is an example of always_ff:

always_ff @(posedge clock iff reset == 0 or posedge reset)

if (reset)


The advantage of using all these new styles of always is that the synthesis tool can check the design intent.

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