clock and reset signal
1. clock signal
Generate the clock signals using a module thread. Program threads are designed to be reactive to the events occurring in the design. Clock signals are the primary cause of these events. The design reacts to clock events.
2. reset signal
reset task should be in program.It will be possible to invoke the reset task in the module from the testbench program threads .
Because modules cannot call program tasks, it will be necessary for each testbench to call the reset program task to reset the DUT . However, this gives the testbenchbetter control over the reset parameters and its coordination with other device
stimuli, not just the clock.
解释一下: semaphore sem=new(1);
Unless a task is declared as automatic, they are not re-entrant. Nonre-entrant tasks are not really an unspecified behavior in SystemVerilog. All simulators have nonre-entrant tasks because every declaration in a SystemVerilog model, except for classes, is
static.By default, no declaration is dynamically allocated upon invocation of a subprogram or entry into a block of code.
When you declare a task or a function, the memory space for its arguments and all other locally declared variables is allocated at compile time. There is a single location for the subprogram and all of its local variables. The memory is not allocated at
runtime each time the task or function is invoked. Every time a subprogram is invoked, thesame memory space is used. This reuse of memory space does not cause problems in functions or in tasks that do not include @, # or wait statements because the local
data space is used in a single invocation. The memory space is no longer in use by the time a second invocation is made. However, if a task contains timing control statements, it may still be active when a second invocation is made.