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UART的FPGA设计源码

文章来源:不详 作者:佚名


该文章讲述了UART的FPGA设计源码.

层文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.uart_1.all;
entity UART is
generic( data_bit:integer:=8;
 total_bit:integer:=10;
 parity_rule:parity:=even;
full_plus_count:bd_count:=bd9600_fpc;
rise_plus_count:bd_count:=bd9600_hpc);

 port (clk:in std_logic;
       reset_n:in std_logic;
       send: in std_logic;
       rxd:in std_logic;
       txd:out std_logic;
       error1:out std_logic;
       send_over:out std_logic;
      recv:out std_logic;
recv_buf:out std_logic_vector(7 downto 0);
send_bus:in std_logic_vector(7 downto 0));
end UART;
architecture rtl of UART is

component  parity_verifier
generic(data_length:integer:=8;
        parity_rule:parity:=even);
 port(
      source:in std_logic_vector(data_length-1 downto 0);
      parity:out std_logic
      );
end component;

component baudrate_generator
generic(full_plus_count:bd_count:=bd9600_fpc;
        rise_plus_count:bd_count:=bd9600_hpc);
 port(clk:in std_logic;
      reset_n:in std_logic;
      ce:in std_logic;
      bdout:out std_logic;
      indicator:out std_logic
      );
end component;

component detector is
port(clk,reset_n,rxd:in std_logic;
     new_data:out std_logic);
end component;

component swith_bus
generic (bus_width:integer:=8);
port(din1,din2:in std_logic_vector(bus_width-1 downto 0);
     sel:in std_logic;
     dout:out std_logic_vector(bus_width-1 downto 0));
end component;

component swith is
port(din1,din2:in std_logic;
     sel:in std_logic;
     dout:out std_logic);
end component;

component shift_register is
generic(total_bit:integer:=10);
port( clk:in std_logic;
      reset_n:in std_logic;
      din:in std_logic;
      regs:out std_logic_vector(total_bit-1 downto 0);
      dout:out std_logic);
end component;

component UART1 IS
 GENERIC(DATA_BIT:INTEGER :=8;
         TOTAL_BIT:INTEGER:=10;
          PARITY_RULE:PARITY:=ev

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